With construction of a large-scale network in recent years, there is a demand for high capacity and high speed of data transmission processing. As a standard of a high speed digital transmission scheme for constructing such a network, there is an optical transport network (OTN) defined in Recommendation G.709 Standard of the International Telecommunication Union Telecommunication Standardization Sector (ITU-T). The OTN transmission scheme defines an optical channel transport unit (OTU) which enables multiple kinds of client signals of different transmission rates to be multiplexed to one signal in a time dividing manner. The OTU is capable of storing multiple kinds of optical-channel data units (ODUs).
As multiple kinds of ODUs, for example, client signals of up to about 1.25 Gbps can be stored in ODU 0, and client signals of up to about 2.5 Gbps can be stored in ODU 1. Also, client signals of up to about 10 Gbps can be stored in ODU 2, client signals of up to about 40 Gbps can be stored in ODU 3, and client signals of up to about 100 Gbps can be stored in ODU 4.
ODU is capable of storing a lower-level ODU. For example, ODU 4 is capable of storing ODU 0, ODU 1, ODU 2, and ODU 3, and ODU 3 is capable of storing ODU 0, ODU 1, and ODU 2. Furthermore, ODU employs a multistage scheme capable of storing lower-level ODUs in a nesting structure in which ODUs are combined in multiple stages. An ODU storing a lower-level ODU is defined as HO (High Order)-ODU, and an ODU not storing a lower-level ODU is defined as LO (Low Order)-ODU.
A demultiplexing device in a transmission apparatus compliant with the OTN demultiplexes HO-ODU in OTU to data of LO-ODU. FIG. 14 is an illustrative diagram illustrating an example of a demultiplexing device in a transmission apparatus. ODU 0 corresponds to a 1 G frame, ODU 2 corresponds to a 10 G frame, ODU 3 corresponds to a 40 G frame, and ODU 4 corresponds to a 100 G frame.
A demultiplexing device 100 illustrated in FIG. 14 includes one 100 G processor 111, two 40 G processors 112, eighteen 10 G processors 113, two hundred and eighty-eight 1 G processors 114, and a SW 115.
The 100 G processor 111 is configured to extract, for example, a multiplex structure identifier (MSI) value indicating a mapping configuration in the 100 G frame when the 100 G frame (ODU 4) is inputted from a 100 G input interface 101A. The 100 G frame includes 80 tributary slots (TS) in the unit of TS. The 100 G processor 111 demultiplexes the 100 G frame to low speed frames based on the extracted MSI value. The low speed frames demultiplexed from the 100 G frame corresponds to, for example, a 40 G frame (ODU 3), a 10 G frame (ODU 2), or a 1 G frame (ODU 0).
Each 40 G processor 112 extracts a MSI value from the 40 G frame when the 40 G frame (ODU 3) is inputted from the 40 G input interface 101B or from the 100 G processor 111. The 40 G frame includes 32 TS. The 40 G processor 112 demultiplexes the 40 G frame to low speed frames based on the extracted MSI value. The low speed frames demultiplexed from the 40 G frame each correspond to, for example, a 10 G frame, or a 1 G frame.
The 10 G processor 113 includes eight 10 G processors 113A, and ten 10 G processors 113B. The 10 G processor 113A extracts the MSI value from the 10 G frame when the 10 G frame (ODU 2) is inputted from the 40 G processor 112. The 10 G frame includes 8 TS. The 10 G processor 113A demultiplexes the 10 G frame to 1 G frames based on the extracted MSI value. The 10 G processor 113B extracts the MSI value from the 10 G frame when the 10 G frame is inputted from the 100 G processor 111 or from the 10 G input interface 101C. The 10 G processor 113B demultiplexes the 10 G frame to 1 G frames based on the extracted MSI value.
The 1 G processor 114 includes sixty-four 1 G processors 114A, sixty-four 1 G processors 114B, eighty 1 G processors 114C, and eighty 1 G processors 114D. The 1 G processor 114A acquires a client signal from the 1 G frame when the 1 G frame is inputted from the 10 G processor 113A. The 1 G processor 114B acquires the client signal from the 40 G frame when the 40 G frame is inputted from the 40 G processor 112. The 1 G processor 114C acquires the client signal from the 1 G frame when the 1 G frame is inputted from the 10 G processor 113B. The 1 G processor 114D acquires the client signal from the 1 G frame when the 1 G frame is inputted from the 100 G processor 111. The SW 115 is a switch configured to output an output signal of the 100 G processor 111, the 40 G processor 112, the 10 G processor 113, or the 1 G processor 114 to output stages by switching them in a predetermined unit.
The demultiplexing device 100 is capable of demultiplexing, for example, the 100 G frame from the 100 G input interface 101A to a client signal via the 100 G processor 111, 40 G processor 112, 10 G processor 113A, and 1 G processor 114A, and outputting the client signal through the SW 115.
The related technique is disclosed by Japanese Laid-open Patent Publication No. 2011-146917, for example.